详细内容
[2]
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3]
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4]
Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide
output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions0n this pin.
[5]
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode0nly).
[6]
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7]
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[8]
Pad provides special analog functionality
7.4 On-chip SRAM
The LPC1766 contains a total of 64 kB0n-chip static RAM memory. This includes the
main 32 kB SRAM, accessible by the CPU and DMA controller0n a higher-speed bus,
and two additional 16 kB each SRAM blocks situated0n a separate slave port0n the AHB
multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
7.5 Memory Protection Unit (MPU)
The LPC1766 has a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place
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