详细内容
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the
system bus and are used similarly to TCM interfaces:0ne bus dedicated for instruction
fetch (I-code) and0ne bus for data access (D-code). The use of two core buses allows for
simultaneous operations if concurrent operations target different devices.
The LPC1766 uses a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are0n different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptable/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,
and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while0ne instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found0n official ARM website.
7.3 On-chip flash program memory
The LPC1766 contains 256 kB of0n-chip flash memory. A new two-port flash accelerator
maximizes performance for use with the two fast AHB-Lite buses.
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