STM32F031K4U6 托盘STM32F769IGT6 托盘
内容简介
Cyclic redundancy check calculation unit (CRC)The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using aconfigurable generator polynomial value and size....
- 型号：STM32F769IGT6
- 供货量：99999PCS
- 品牌：st
- 发货地：广东深圳
- 发货期：1-3天
- 价格：￥18.2元/PCS
详细内容
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
•
VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
•
VDDA = from VDD to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
are used). It is provided externally through VDDA pin. The VDDA voltage level must be
always greater or equal to the VDD voltage level and must be established first.
•
VDDIO2 = 1.65 to 3.6 V: external power supply for marked I/Os. VDDIO2 is provided
externally through the VDDIO2 pin. The VDDIO2 voltage level is completely independent
from VDD or VDDA, but it must not be provided without a valid supply0n VDD. The
VDDIO2 supply is monitored and compared with the internal reference voltage
(VREFINT). When the VDDIO2 is below this threshold, all the I/Os supplied from this rail
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details0n how to connect power pins, refer to Figure 12: Power supply scheme.
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•
The POR monitors0nly the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
•
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
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