STM32F103VCT6STM8S207R8T6 托盘

内容简介

Boot modesAt startup, boot pins are used to select0ne of three boot options:●Boot from user Flash: you have an option to boot from any of two memory banks. Bydefault, boot from Fl...

型号：STM32F103VCT6
供货量：99999PCS
品牌：st
发货地：广东深圳
发货期：1-3天
价格：￥7.9元/PCS

详细内容

Boot modes

At startup, boot pins are used to select0ne of three boot options:

●

Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

memory bank 2 by setting a bit in the option bytes.

●

Boot from system memory

●

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1.

2.3.11

Power supply schemes

●

VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.

●

VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC

is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

●

VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when VDD is not present.

For more details0n how to connect power pins, refer to Figure 12: Power supply scheme.

2.3.12

Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be

generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

VPOR/PDR and VPVD.

2.3.13

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

●

LPR is used in the Stop modes.

●

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode

本文来源：//www.kids-shops.com/repeat/69855024.html

免责声明：以上信息由会员自行提供，内容的真实性、准确性和合法性由发布会员负责，一步电子网对此不承担任何责任。汇款需谨慎，请注意调查核实，一步电子网不涉及用户间产生的法律纠纷，纠纷由您自行协商解决。

手机访问"STM32F103VCT6STM8S207R8T6 托盘"更方便扫一扫手机查看微官网和产品信息


扫一扫, 进入微官网		扫一扫, 手机查看产品

相关文章